Plasma processing apparatus

ABSTRACT

A plasma processing apparatus may include a lower electrode supporting a wafer; a focus ring surrounding an edge of the lower electrode and having a ring shape; and an edge ring disposed in a position lower than a position of the focus ring. The focus ring may include a lower region and an upper region disposed on the lower region, and the upper region increases in electrical conductivity as the upper region is closer to the lower region.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2019-0015640 filed on Feb. 11, 2019 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

The disclosure relates to a plasma processing apparatus.

Generally, a semiconductor device is manufactured through a plurality of unit processes including a thin film deposition process, a dry etching process, or the like. The dry etching process is mainly performed in a semiconductor manufacturing apparatus in which a plasma reaction is induced. With the miniaturization and high integration of semiconductor products, the characteristics of manufactured semiconductor devices have increasingly been influenced by non-uniformities of the dry etching process.

SUMMARY

An aspect of the disclosure is to provide a plasma processing apparatus in which an incident angle of ions in an edge region of a wafer may be kept substantially constant even when a focus ring is consumed.

In accordance with an aspect of the disclosure, a plasma processing apparatus includes a lower electrode configured to support a wafer on an upper surface of the lower electrode; a focus ring surrounding an edge of the lower electrode and having a ring shape; and an edge ring disposed in a position lower than a position of the focus ring, wherein the focus ring includes a lower region and an upper region disposed on the lower region, wherein an electrical conductivity of a first portion of the upper region is smaller than an electrical conductivity of a second portion of the upper region that is closer to the lower region than the first portion.

The first portion may include a first layer and the second portion may include a second layer, and the second layer may be stacked on the lower region and the first layer is stacked on the second layer.

The first layer and the second layer may include a same semiconductor material, and a dopant concentration of the second layer may be larger than a dopant concentration of the first layer.

The semiconductor material may include silicon or silicon carbide.

The first layer may include a first semiconductor material and the second layer may include a second semiconductor material different from the first semiconductor material.

An electrical conductivity of the upper region may gradually increase from a first side of the upper region to a second side of the upper region that is closer to the lower region than the first side.

The upper region may include a semiconductor material, and a dopant concentration in the upper region may gradually increase from the first side to the second side.

An electrical conductivity of the lower region may be greater than a maximum electrical conductivity of the upper region.

A boundary between the lower region and the upper region may be located higher than an upper surface of the lower electrode.

The upper region may include a side surface adjacent to the wafer, the side surface having a slope such that the side surface is not perpendicular to the upper surface of the lower electrode.

In accordance with an aspect of the disclosure, a plasma processing apparatus includes a process chamber; a lower electrode disposed in the process chamber, an upper surface of the lower electrode being configured to support a wafer; a focus ring surrounding an upper edge of the lower electrode; and an edge ring surrounding a lower edge of the lower electrode and supporting the focus ring, wherein the focus ring includes a lower region and an upper region disposed on the lower region, wherein an electrical conductivity of a first portion of the upper region is smaller than an electrical conductivity of a second portion of the upper region that is closer to the lower region than the first portion, and wherein the lower region has a greater electrical conductivity than a maximum electrical conductivity of the upper region.

The first portion may include a first layer stacked on the lower region and the second portion may include a second layer stacked on the first layer.

The first layer and the second layer may include a same semiconductor material, a dopant concentration of the second layer may be larger than a dopant concentration of the first layer, and a dopant concentration of the lower region may be greater than a maximum dopant concentration of the upper region.

The first layer may include a first semiconductor material and the second layer may include a second semiconductor material different from the first semiconductor material.

An electrical conductivity of the upper region may gradually increase from a first side of the upper region to a second side of the upper region that is closer to the lower region than the first side.

The upper region and the lower region may include a same semiconductor material, a dopant concentration in the upper region may gradually increase from the first side to the second side, and the lower region may have a greater dopant concentration than a maximum dopant concentration of the upper region.

A boundary between the lower region and the upper region may be located higher than the upper surface of the lower electrode, and may be located lower than an upper surface of the wafer.

In accordance with an aspect of the disclosure, a plasma processing apparatus includes a process chamber; a lower electrode disposed in the process chamber, an upper surface of the lower electrode being configured to support a wafer; a focus ring surrounding an upper edge of the lower electrode, the focus ring including a semiconductor material; an insulation ring surrounding an outer peripheral surface of the focus ring, the insulation ring including an insulating material; and an edge ring disposed in a position lower than a position of the focus ring and a position of the insulation ring, wherein the focus ring includes a lower region and an upper region disposed on the lower region, wherein an electrical conductivity of a first portion of the upper region is smaller than an electrical conductivity of a second portion of the upper region that is closer to the lower region than the first portion, and wherein the lower region has a greater electrical conductivity than a maximum electrical conductivity of the upper region.

The first portion may include a first layer and the second portion may include a second layer, the first layer and the second layer may include a same semiconductor material, and a dopant concentration in the first layer may be smaller than a dopant concentration in the second layer.

An electrical conductivity of the upper region may gradually increase from a first side of the upper region to a second side of the upper region that is closer to the lower region than the first side, and a dopant concentration in the first portion may be smaller than a dopant concentration in the second portion.

BRIEF DESCRIPTION OF DRAWINGS

The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description, taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a schematic view of a plasma processing apparatus according to an embodiment.

FIG. 2 is an enlarged view of ‘A’ region of FIG. 1.

FIGS. 3 and 4 are views illustrating a plasma processing apparatus according to embodiments.

FIGS. 5 to 9 are views illustrating simulation results of an embodiment and a comparative example.

DETAILED DESCRIPTION

Hereinafter, a plasma processing apparatus according to embodiments of the disclosure will be described with reference to the accompanying drawings.

FIG. 1 is a schematic view of a plasma processing apparatus according to an embodiment.

Referring to FIGS. 1 and 2, a plasma processing apparatus according to an embodiment may include a process chamber 60, a lower electrode 10 disposed in the process chamber 60 and supporting a wafer W on an upper surface of the lower electrode 10, an edge ring 40 surrounding the lower electrode 10, a focus ring 20 disposed on the edge ring 40, an insulation ring 30 surrounding the focus ring 20, an isolator 50 disposed in a position lower than a position of the lower electrode 10 and the edge ring 40, an upper electrode 70 disposed above the lower electrode 10 to face the lower electrode 10, and the like. Here, the terms “upper”, “lower”, “higher”, “above”, etc. may be defined such that an element that is “lower” than another element is positioned closer to the isolator 50 than the other element. Similarly, an element that is “higher” than or “above” another element may be positioned closer to the upper electrode 70 than the other element.

The lower electrode 10 may support an object to be processed, e.g., the wafer W. For example, the lower electrode 10 may be an electrostatic chuck. For example, the lower electrode 10 may produce an electrostatic force to position the wafer W on the lower electrode 10.

The lower electrode 10 may have a shape similar to that of the wafer W. For example, an upper surface of the lower electrode 10 may be formed to have a circular shape. As shown in FIG. 2, the lower electrode 10 may include an upper portion 11 facing the wafer W, and a lower portion 12 facing the isolator 50. A diameter of the lower portion 12 of the lower electrode 10 may be different from a diameter of the upper portion 11 of the lower electrode 10. For example, the diameter of the lower portion 12 of the lower electrode 10 may be greater than the diameter of the upper portion 11 of the lower electrode 10. In this case, a side surface of the lower electrode 10 may have a step difference according to the difference in diameter between the upper portion 11 an the lower portion 12. The disclosure is not limited thereto, and the diameter of the upper portion 11 of the lower electrode 10 may be the same as the diameter of the lower portion 12 of the lower electrode 10.

The wafer W may completely cover the upper portion 11 of the lower electrode 10. A portion of the wafer W may protrude beyond an edge of the upper portion 11 of the lower electrode 10 in a radial direction. For example, a diameter of the upper portion 11 of the lower electrode 10 may be smaller than a diameter of the wafer W. This configuration may prevent the lower electrode 10 from being damaged when the wafer W is subject to a plasma treatment process, for example, a dry etching process. An upper surface of the wafer W may be exposed to plasma, but the upper surface of the lower electrode 10 may not be exposed to plasma.

The lower electrode 10 may support a lower surface of the wafer W, and may cool the wafer W on which the plasma treatment process is performed, at the same time. When ions in the plasma are supplied to the wafer W, a surface of the wafer W may be etched, and a surface temperature of the wafer W may rise sharply, at the same time. When the surface temperature of the wafer W increases excessively, the wafer W may be deformed or damaged. In order to prevent this, the lower electrode 10 may have a channel through which a coolant flows, and the coolant may flow through the channel to control the surface temperature of the wafer W disposed on the lower electrode 10. As the coolant, for example, helium (He) or the like may be used, but it is not limited thereto.

The focus ring 20 may be disposed to surround an edge of the wafer W. The focus ring 20 may surround a portion of the lower electrode 10 on which the wafer W is disposed. For example, the focus ring 20 may have a ring shape surrounding the upper portion 11 of the lower electrode 10. A portion of the focus ring 20 may be disposed in a position lower than a position of the edge of the wafer W, and may cover a side surface of the upper portion 11 of the lower electrode 10. In other words, a portion of the focus ring 20 may be positioned underneath the protruding edge of the wafer W. The portion of the focus ring 20 may contact the side surface of the upper portion 11 of the lower electrode 10. At the same time, the focus ring 20 may cover at least a portion of an upper surface of the lower portion 12 of the lower electrode 10. The focus ring 20 may prevent the lower electrode 10 from being damaged in the plasma treatment process.

When the focus ring 20 includes, for example, an electrically conductive material, the focus ring 20 may have properties of an electrode. When radio frequency (RF) power is applied to the lower electrode 10 and/or the upper electrode 70 to form an electric field, the focus ring 20 may function to expand a formation region of the electric field to uniformly process the wafer W. Further, the focus ring 20 may function to confine a formation region of the plasma within a specific region.

The focus ring 20 may be made of a semiconductor material such as, for example, silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), or the like. Since the focus ring 20 may be directly exposed to the plasma during the plasma treatment process, an upper portion of the focus ring 20 may be etched as the plasma treatment process is repeated. As the plasma treatment process is repeated, a level of the upper surface of the focus ring 20 may be gradually lowered.

In an embodiment of the disclosure, the focus ring 20 may include a lower region 22 and an upper region 24 disposed on the lower region 22, wherein the upper region 24 may increase in electrical conductivity as the upper region is closer to the lower region 22. In other words, an electrical conductivity of a first portion of the upper region 24 may be smaller than an electrical conductivity of a second portion of the upper region 24 that is closer to the lower region 22 than the first portion. The upper region 24 of the focus ring 20 may include a plurality of layers, stacked on the lower region 22, in which electric conductivity increases discontinuously as the upper region is closer to the lower region 22. In other words, the upper region 24 may include a first layer and a second layer, and the second layer may be stacked on the lower region 22 and the first layer may be stacked on the second layer. The upper region 24 may include a first upper layer 24 a, a second upper layer 24 b, a third upper layer 24 c, and a fourth upper layer 24 d, sequentially increasing in electrical conductivity. In FIG. 2, the upper region 24 is illustrated as consisting of four (4) layers having different electrical conductivities, but the disclosure is not limited to that illustrated in FIG. 2. For example, the upper region 24 may include five (5) or more layers having different electrical conductivities. For example, the upper region 24 may include two (2) layers or three (3) layers having different electrical conductivities. Electrical conductivity of the lower region 22 may be greater than a maximum electrical conductivity of the upper region 24. For example, electrical conductivities of the first upper layer 24 a, the second upper layer 24 b, the third upper layer 24 c, and the fourth upper layer 24 d may range from 0.005 to 0.01 ohm-1 cm-1, and electrical conductivity of the lower region 22 may range from 0.05 to 1 ohm-1 cm-1. However, the electrical conductivities of the first upper layer 24 a, the second upper layer 24 b, the third upper layer 24 c, and the fourth upper layer 24 d, and the electrical conductivity of the lower region 22 are not limited to the above-described ranges.

The first upper layer 24 a, the second upper layer 24 b, the third upper layer 24 c, and the fourth upper layer 24 d may be made of the same semiconductor material, and dopant concentrations of the first upper layer 24 a, the second upper layer 24 b, the third upper layer 24 c, and the fourth upper layer 24 d may increase as the first upper layer 24 a, the second upper layer 24 b, the third upper layer 24 c, and the fourth upper layer 24 d are closer to the lower region 22. In other words, an upper layer that is closer to the lower region 22 may have a dopant concentration higher than that of an upper layer that is farther from the lower region 22. The lower region 22 may be made of the same semiconductor material as the upper region 24, and a dopant concentration of the lower region 22 may be greater than a maximum dopant concentration of the upper region 24. A dopant concentration of the lower region 22 may be greater than a dopant concentration of the fourth upper layer 24 d which is shown in FIG. 2 as being closest to the lower region 22. The focus ring 20 may be made of, for example, silicon carbide (SiC), and the dopant may be nitrogen (N), phosphorus (P), boron (B), or the like. Alternatively, the focus ring 20 may be made of, for example, silicon (Si), and the dopant may be arsenic (As), phosphorus (P), boron (B), aluminum (Al), or the like.

The first upper layer 24 a, the second upper layer 24 b, the third upper layer 24 c, and the fourth upper layer 24 d may be made of different semiconductor materials, and the electrical conductivities of the first upper layer 24 a, the second upper layer 24 b, the third upper layer 24 c, and the fourth upper layer 24 d may increase as the first upper layer 24 a, the second upper layer 24 b, the third upper layer 24 c, and the fourth upper layer 24 d are closer to the lower region 22. The lower region 22 may be made of a semiconductor material having a greater electrical conductivity than the fourth upper layer 24 d.

A boundary between the lower region 22 and the upper region 24 of the focus ring 20 may be located higher than the upper surface of the lower electrode 10. The boundary between the lower region 22 and the upper region 24 of the focus ring 20 may be located lower than the upper surface of the wafer W. Side surfaces of the upper region 24 of the focus ring 20 may be perpendicular to the upper or lower surface of the focus ring 20.

A plasma processing apparatus according to an embodiment of the disclosure may employ a focus ring 20, such that an incident angle of ions in an edge region of a wafer W may be maintained substantially constant even as the focus ring 20 is consumed. This will be described later with reference to FIGS. 5 to 9.

An insulation ring 30 may have a ring shape to surround an outer peripheral surface of the focus ring 20. The insulation ring 30 may include a different material than the focus ring 20. More specifically, the insulation ring 30 may include a material that may have etching resistance in an etching process using plasma. In addition, the insulation ring 30 may include an insulating material. For example, when the focus ring 20 includes silicon, the insulation ring 30 may include quartz.

An edge ring 40 may have a ring shape surrounding a lower portion 12 of a lower electrode 10. The edge ring 40 may be disposed in a position lower than a position of the focus ring 20 and the insulation ring 30, and may support the focus ring 20 and the insulation ring 30. The edge ring 40 may include a metallic material. More specifically, the edge ring 40 may include aluminum, but the disclosure is not limited thereto.

Since the focus ring 20 may be directly exposed to plasma during a plasma treatment process for a wafer W, a temperature of the focus ring 20 may increase. As described above, a channel through which a coolant for cooling the wafer W flows may be formed in the lower electrode 10. By using this, an increase in temperature of the wafer W during the plasma process may be controlled, but an upper surface of the focus ring 20 may not be cooled. The upper surface of the focus ring 20 may therefore have a different temperature from a surface of the wafer W, and an imbalance may occur in the plasma provided to surfaces of the wafer W and the focus ring 20. Plasma may also be provided on an upper surface of the insulation ring 30 during the plasma treatment process for the wafer W. A temperature of the insulation ring 30 provided with the plasma may increase. When the insulation ring 30 is heated, an imbalance between a heated temperature of the insulation ring 30 and a temperature of an upper surface of the wafer W may occur in a manner similar to that of the focus ring 20, and an imbalance may occur in the plasma supplied to surfaces of the wafer W and the insulation ring 30. Therefore, a channel of a coolant may be further included in the edge ring 40 to cool the focus ring 20 and the insulation ring 30 in a manner similar to that of the channel of the coolant in the lower electrode 10 for cooling the wafer W.

The insulation ring 30 may also be supported by a support ring 35. The support ring 35 may contact a portion of a lower surface of the insulation ring 30. As illustrated in FIG. 1, the support ring 35 may be disposed to surround an outer peripheral surface of the edge ring 40. The support ring 35 may block the plasma from being provided to a side portion of the edge ring 40. The support ring 35 may include materials having etching resistance to plasma etching gas, and may include, for example, quartz, but is not limited thereto. The support ring 35 may contact at least a portion of an isolator 50, and may also be supported by the isolator 50.

The isolator 50 may be disposed in a position lower than a position of the lower electrode 10, the edge ring 40, and the support ring 35. The isolator 50 may support the lower electrode 10, the edge ring 40, and the support ring 35. The isolator 50 may include an insulating material, and may include, for example, a ceramic.

An upper electrode 70 may be disposed in a process chamber 60 to face the lower electrode 10.

RF power may be applied to the lower electrode 10 by a second power source 90 during the plasma treatment process using a plasma processing apparatus according to an embodiment. The upper electrode 70 may receive RF power from a first power source 80, and may be synchronized with the lower electrode 10, to excite source gas supplied to the process chamber 60 to form plasma.

A plasma processing apparatus according to an embodiment may include a processing chamber 60 that provides a space for performing a plasma treatment process for the wafer W, for example, a dry etching process.

The process chamber 60 may include an inlet 101 and an outlet 100, which may be selectively opened and closed under control. The source gas used in the plasma treatment process may be supplied to the process chamber 60 through the inlet 101. A by-product generated by the plasma treatment process may be discharged through the outlet 100. In FIG. 1, a single inlet 101 and a single outlet 100 are illustrated as being formed in the process chamber 60, respectively, but the disclosure is not limited thereto. The process chamber 60 may include a plurality of inlets 101 and outlets 100, respectively.

FIGS. 3 and 4 are views illustrating a plasma processing apparatus according to embodiments of the disclosure. Since focus rings illustrated in FIGS. 3 and 4 are similar to a focus ring illustrated in FIG. 2, only the differences between FIGS. 3 and 4, and FIG. 2 will be described below.

Referring to FIG. 3, a focus ring 20′ may be made of a semiconductor material such as, for example, silicon (Si), silicon carbide (SiC), or gallium arsenide (GaAs).

The focus ring 20′ may include a lower region 22 and an upper region 24′ disposed on the lower region 22, wherein the electrical conductivity of the upper region 24′ may increase toward to the lower region 22. The electric conductivity of the upper region 24′ of the focus ring 20 may gradually increase toward to the lower region 22.

The upper region 24′ may be made of a single semiconductor material, and a dopant concentration in the upper region may gradually increase toward to the lower region 22. The lower region 22 may be made of the same semiconductor material as the upper region 24′, and a dopant concentration in the lower region 22 may be greater than a maximum dopant concentration of the upper region 24′. The focus ring 20′ may be made of, for example, silicon carbide (SiC), and the dopant may be nitrogen (N), phosphorus (P), boron (B), or the like. Alternatively, the focus ring 20′ may be made of, for example, silicon (Si), and the dopant may be arsenic (As), phosphorus (P), boron (B), aluminum (Al), or the like.

Referring to FIG. 4, in a different manner to FIG. 2, a side surface of an upper region 24″ of a focus ring 20″ adjacent to a wafer W may have a slope relative to an upper or lower surface of the focus ring 20″. In other words, the side surface of the upper region 24″ may not be perpendicular to the upper or lower surface of the focus ring 20″. A width of the upper region 24″ may become smaller as the upper region is further away from a lower region 22″. A portion of the lower region 22″ adjacent the upper region 24″ may also have a sloped side surface. Widths of a first upper layer 24 a″, a second upper layer 24 b″, a third upper layer 24 c″, and a fourth upper layer 24 d″ may become smaller as the upper region is further away from the lower region 22″. In an embodiment, in a different manner to that illustrated in FIG. 4, a side surface of the upper region 24″ of the focus ring 20″ adjacent to an insulation ring 30 may be sloped with respect to an upper or lower surface of the focus ring 20″, and a side surface of the upper region 24″ of the focus ring 20″ adjacent to the wafer W may not have a slope with respect to an upper or lower surface of the focus ring 20″. In this case, a width of the upper region 24″ may become smaller as the upper region is further away from the lower region 22″. In an embodiment, in a different manner to that illustrated in FIG. 4, both the side surface of the upper region 24″ of the focus ring 20″ adjacent to the wafer W and the side surface of the upper region 24″ of the focus ring 20″ adjacent to the insulation ring 30 may be sloped with respect to an upper or lower surface of the focus ring 20″. In this case, a width of the upper region 24″ may become smaller as the upper region is further away from the lower region 22″.

FIGS. 5 to 9 are views illustrating simulation results of an embodiment and a comparative example.

FIG. 5 illustrates changes in a tilting angle of ions incident on an edge portion of a wafer, depending on an etching depth of a focus ring, with respect to an embodiment and a comparative example.

Referring to FIG. 5, in a case of a comparative example employing a focus ring 22′ (see FIGS. 8 and 9) having a single electrical conductivity, as an etching depth of the focus ring 22′ increases, a tilting angle of ions may change greatly. In a case of an embodiment in which a focus ring 20 (see FIGS. 6 and 7) made up of an upper region 24 and a lower region 22 including a plurality of layers having different electric conductivities is employed, it can be seen that a tilting angle of ions may be maintained almost constant even when an etching depth of the focus ring 20 increases. A negative (−) value of the tilting angle means that ions are sloped obliquely in a direction from a central portion of a wafer toward an edge portion of a wafer. Meanwhile, a positive (+) value of the tilting angle means that ions incident on an edge portion of a wafer are sloped obliquely in a direction from the edge portion of the wafer toward the central portion of the wafer.

FIG. 6 illustrates a case in which a focus ring 20 including an upper region 24 and a lower region 22 including a plurality of layers having different electrical conductivities according to an embodiment is used, and a simulation result for a state in which an etching depth of the focus ring 20 is 0 mm, for example, an initial state of the focus ring 20. Equipotential lines indicated by dotted lines may be uniformly formed without being distorted near the focus ring 22, and may be substantially parallel to an upper surface of a wafer W across the upper surface of the wafer W and at an edge portion of the wafer W. As a result, ions incident on the edge portion of the wafer W may be incident at an angle of about (−) 0.1 degrees.

FIG. 7 illustrates a case in which a focus ring 20 including an upper region 24 and a lower region 22 according to an embodiment is used, and a simulation result for a state in which an etching depth of the focus ring 20 is 1.2 mm. The upper region 24 of the focus ring 20 may be completely etched, and equipotential lines may be still substantially parallel to an upper surface of a wafer W across the upper surface of the wafer W and at an edge portion of the wafer W. As a result, ions incident on the edge portion of the wafer W may be incident in an almost vertical direction.

FIG. 8 illustrates a case in which a focus ring 22′ according to a comparative example is used, and a simulation result for a state in which an etching depth of the focus ring 22′ is 0 mm, for example, an initial state of the focus ring 22′. Equipotential lines indicated by dotted lines may be distorted and unevenly formed near the focus ring 22′, and may not be parallel to an upper surface of a wafer W at an edge portion of the wafer W. As a result, ions incident on the edge portion of the wafer W may be incident at an angle of about (−) 0.9 degrees.

FIG. 9 illustrates a case in which a focus ring 22′ according to a comparative example is used, and a simulation result for a state in which an etching depth of the focus ring 22′ is 0.9 mm. Although the focus ring 22′ is etched so as not to distort equipotential lines indicated by dotted lines near the focus ring 22′, comparing to in FIG. 8, the equipotential lines may still not be parallel to an upper surface of the wafer W on the edge of the wafer W. As a result, ions incident on the edge portion of the wafer W may be incident at an angle of about (−) 0.35 degrees.

According to an embodiment, even when the focus ring may be consumed in the plasma processing apparatus, the incident angle of the ions in the edge region of the wafer may be kept constant.

The various advantages and effects of the disclosure may not be limited to the above description, and can be more easily understood in the course of describing specific embodiments.

While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the disclosure as defined by the appended claims. 

What is claimed is:
 1. A plasma processing apparatus comprising: a lower electrode configured to support a wafer on an upper surface of the lower electrode; a focus ring surrounding an edge of the lower electrode and having a ring shape; and an edge ring disposed in a position lower than a position of the focus ring, wherein the focus ring comprises a lower region and an upper region disposed on the lower region, wherein an electrical conductivity of a first portion of the upper region is smaller than an electrical conductivity of a second portion of the upper region that is closer to the lower region than the first portion.
 2. The plasma processing apparatus according to claim 1, wherein the first portion comprises a first layer and the second portion comprises a second layer, and wherein the second layer is stacked on the lower region and the first layer is stacked on the second layer.
 3. The plasma processing apparatus according to claim 2, wherein the first layer and the second layer comprise a same semiconductor material, and wherein a dopant concentration of the second layer is larger than a dopant concentration of the first layer.
 4. The plasma processing apparatus according to claim 3, wherein the semiconductor material comprises silicon or silicon carbide.
 5. The plasma processing apparatus according to claim 2, wherein the first layer comprises a first semiconductor material and the second layer comprises a second semiconductor material different from the first semiconductor material.
 6. The plasma processing apparatus according to claim 1, wherein an electrical conductivity of the upper region gradually increases from a first side of the upper region to a second side of the upper region that is closer to the lower region than the first side.
 7. The plasma processing apparatus according to claim 6, wherein the upper region comprises a semiconductor material, and wherein a dopant concentration in the upper region gradually increases from the first side to the second side.
 8. The plasma processing apparatus according to claim 1, wherein an electrical conductivity of the lower region is greater than a maximum electrical conductivity of the upper region.
 9. The plasma processing apparatus according to claim 1, wherein a boundary between the lower region and the upper region is located higher than an upper surface of the lower electrode.
 10. The plasma processing apparatus according to claim 1, wherein the upper region comprises a side surface adjacent to the wafer, the side surface having a slope such that the side surface is not perpendicular to the upper surface of the lower electrode.
 11. A plasma processing apparatus comprising: a process chamber; a lower electrode disposed in the process chamber, an upper surface of the lower electrode being configured to support a wafer; a focus ring surrounding an upper edge of the lower electrode; and an edge ring surrounding a lower edge of the lower electrode and supporting the focus ring, wherein the focus ring comprises a lower region and an upper region disposed on the lower region, wherein an electrical conductivity of a first portion of the upper region is smaller than an electrical conductivity of a second portion of the upper region that is closer to the lower region than the first portion, and wherein the lower region has a greater electrical conductivity than a maximum electrical conductivity of the upper region.
 12. The plasma processing apparatus according to claim 11, wherein the first portion comprises a first layer stacked on the lower region and the second portion comprises a second layer stacked on the first layer.
 13. The plasma processing apparatus according to claim 12, wherein the first layer and the second layer comprise a same semiconductor material, wherein a dopant concentration of the second layer is larger than a dopant concentration of the first layer, and wherein a dopant concentration of the lower region is greater than a maximum dopant concentration of the upper region.
 14. The plasma processing apparatus according to claim 12, wherein the first layer comprises a first semiconductor material and the second layer comprises a second semiconductor material different from the first semiconductor material.
 15. The plasma processing apparatus according to claim 11, wherein an electrical conductivity of the upper region gradually increases from a first side of the upper region to a second side of the upper region that is closer to the lower region than the first side.
 16. The plasma processing apparatus according to claim 15, wherein the upper region and the lower region comprise a same semiconductor material, wherein a dopant concentration in the upper region gradually increases from the first side to the second side, and wherein the lower region has a greater dopant concentration than a maximum dopant concentration of the upper region.
 17. The plasma processing apparatus according to claim 11, wherein a boundary between the lower region and the upper region is located higher than the upper surface of the lower electrode, and is located lower than an upper surface of the wafer.
 18. A plasma processing apparatus comprising: a process chamber; a lower electrode disposed in the process chamber, an upper surface of the lower electrode being configured to support a wafer; a focus ring surrounding an upper edge of the lower electrode, the focus ring comprising a semiconductor material; an insulation ring surrounding an outer peripheral surface of the focus ring, the insulation ring comprising an insulating material; and an edge ring disposed in a position lower than a position of the focus ring and a position of the insulation ring, wherein the focus ring comprises a lower region and an upper region disposed on the lower region, wherein an electrical conductivity of a first portion of the upper region is smaller than an electrical conductivity of a second portion of the upper region that is closer to the lower region than the first portion, and wherein the lower region has a greater electrical conductivity than a maximum electrical conductivity of the upper region.
 19. The plasma processing apparatus according to claim 18, wherein the first portion comprises a first layer and the second portion comprises a second layer, wherein the first layer and the second layer comprise a same semiconductor material, and wherein a dopant concentration in the first layer is smaller than a dopant concentration in the second layer.
 20. The plasma processing apparatus according to claim 18, wherein an electrical conductivity of the upper region gradually increases from a first side of the upper region to a second side of the upper region that is closer to the lower region than the first side, and wherein a dopant concentration in the first portion is smaller than a dopant concentration in the second portion. 